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Intel Sandy Bridge. Microarchitecture

Intel Sandy Bridge microarchitecture overview

Processor microarchitecture. Processor pipeline

Shortly speaking, Sandy Bridge microarchitecture — it is and modified and significantly re-worked Intel Nahalem microarchitecture with several innovations. To see the difference in a complex super-scalar hyper pipelined microarchitecture of modern Intel’s processors, we have to be patient enough to go into the question of details of every single processor block at large. We will start from the main micro-processor block — the core.

Processor pipeline

The main principle of pipeline functioning is the same as it was in Nehalem:

Modern Intel’s processor pipeline block diagram

L2 Cache instructions get to the Front end, which is responsible for data prefetching, branch prediction and operation decoding. In other words, the Front End converts complex instructions to simple ones — micro-operations (Uops).

Uops, as a results of decoded caches instructions, get to resource dispatcher (In Order Allocation, Rename, Retirement). Here, all the computational resources are distributed, registers are renamed as well as the state of all Uops that are processed is checked.

After the processor is ready to execute Uops, they are sent to out-of-order machine ensuring the optimal order of Uop execution.

Starting from this very moment, Uops can be processed in a free way and the execution queue is regulated by the scheduler. As Uops in the queue are ready to fire, the scheduler sends them to corresponding execution blocks that are grouped by type.

The changes in the core architecture has also affected the pipeline blocks. Let’s take a closer look.

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