Intel Sandy Bridge. Microarchitecture

Front End

Back to Nehalem architecture again — pipeline Front End has four consecutive levels of data processing:

Despite some serious enchantments in Nehalem architecture, there are still some drawbacks left in processor pipeline functioning: limited bandwidth and significant performance loss in case of mistakes in branch prediction choice.

The Front End now features one additional unit — Uops Cache (L0):

Before another Uops can be processed, Sandy Bridge’s fetch hardware checks if the instruction is in the L0 cache. If it is then instruction decoding is canceled and results is read to Uops cache.

The advantages of Uops cache are as follows:

• Up to 80% of Uops are taken from cache without re-compilation
• Decoded Uops are used multiple times
• Increased decoder operation speed
• Significant energy savings of the Front end
• Front End window is larger by 32 bites per clock

Together with the introduction of new Uops cache Intel has also redesigned Branch Prediction Unit (BPU) completely. BPU allows instruction and memory data prefetch as well as execution of instructions located after the conditional jump before it (jump) is done.

The majority of modern branch predictors have its predictions based on global history which includes execution results of some jump commands met earlier. Traditional prediction algorithms has quiet a limited history size, because by adding one byte to history results in double the size of a predictor. A combination of different prediction techniques coupled with new ways of history records gives the opportunity to considerably enlarge prediction efficiency without serious unit changes which is implemented in Sandy Bridge.

A list of improvements done to new BPU:

• Less wrong predictions
• Doubled amount of targets
• More effective history organization
• Longer behavior dependence history

As we see, Intel’s engineers pay close attention to drawbacks of the pipeline and they are doing quite well, at least in theory.