TSMC announced today that 28nm support within the Open Innovation Platform™ (OIP) design infrastructure is fully delivered, as demonstrated by 89 new 28nm designs scheduled to tapeout. The company will also introduce OIP enhancements, including the delivery of Reference Flow 12.0 and Analog/Mixed Signal (AMS) Reference Flow 2.0 at the upcoming Design Automation Conference (DAC) in San Diego California.
TSMC’s 28nm design ecosystem is ready today with foundation collateral such as DRC, LVS and PDKs; foundation IP, including standard cell libraries, standard I/O, efuse and memory compilers; and standard interface IP such as USB, PCI and DDR/LPDDR. Customers can download these materials at TSMC Online. Collaboration with the EDA community for 28nm has been equally thorough in order to achieve tool consistency for improved design results. One example is a unified DFM engine for 28nm now in use by Cadence, Synopsys and Mentor.
Reference Flow 12.0 features various enhancements in: two-and-a-half dimensional and three dimensional integrated circuits (2.5-D/3-D ICs) using silicon interposer and through silicon via (TSV) technologies; 28nm model-based simulation DFM speed-up; and advanced Electronic System Level (ESL) design initiative enabling TSMC’s process technology PPA (power, performance, and area) to be integrated into system level design. In addition, Reference Flow 12.0 will disclose TSMC’s 20nm Transparent Double Patterning design solution for the first time as part of the on-going build up of 20nm design capability within OIP.
AMS Reference Flow 2.0 offers an advanced multi-partner AMS design flow addressing the growing complexity of 28nm process effects and design challenges for superior DFM and RDR compliance and reliability.
Cliff Hou, TSMC Senior Director, Design and Technology Platform, said:
TSMC customers can immediately take advantage of our 28nm advanced technology and manufacturing capacity while preparing for 20nm in the near future. We have enabled customers to achieve their product design goals by closely collaborating with our EDA and IP partners to deliver a solid 28nm design ecosystem. In addition, the introduction of Reference Flow 12.0 and AMS Reference Flow 2.0 address critical design issues for the next generation of 28nm and 20nm applications.